Coupling-aware high-level interconnect synthesis [IC layout]

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2004-01, Vol.23 (1), p.157-164
• Main Authors: Lyuh, C.-G., Kim, T., Kim, K.-W.
• Format: Article
• Language: English
• Subjects: Capacitance; Coupling circuits; Energy consumption; Integrated circuit synthesis; Microarchitecture; Power dissipation; Power system interconnection; Signal synthesis; Studies; System-on-a-chip; Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2003.819892

Ultra-deep submicron technology and system-on-chip have resulted in a considerable portion of power dissipated on buses, in which the major sources of the power dissipation are: 1) the self transition activities on the signal lines and 2) the coupled transition activities of the lines. However, there has been no easy way of optimizing 1 and 2 simultaneously at an early stage of the synthesis process. In this paper, we propose a new (on-chip) bus synthesis algorithm to minimize the total sum of 1 and 2 in the microarchitecture synthesis. Specifically, unlike the previous approaches in which 1 and 2 are minimized sequentially without any interaction between them, or only one of them is minimized, we, given a scheduled dataflow graph to be synthesized, minimize 1 and 2 simultaneously by formulating and solving the two important issues in an integrated fashion: binding data transfers to buses and determining a (physical) order of signal lines in each bus, both of which are the most critical factors that affect the results of 1 and 2. Experimental results on a number of benchmark problems show that the proposed integrated low-power bus synthesis algorithm reduces power consumption by 24.8%, 40.3%, and 18.1% on average over those in (Chang and Pedram 1995, for minimizing 1 only), (Shin and Sakurai 2001, for 2 only) and (Shin and Sakurai 2001 and Chang and Pegram 1995, for 1 and then 2), respectively.