Simultaneous Floorplan and Buffer-Block Optimization

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2004-05, Vol.23 (5), p.694-703
Main Authors: Jiang, I.H.-R., Chang, Y.-W., Jou, J.-H., Chao, K.-Y.
Format: Article
Language:English
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ISSN:0278-0070
DOI:10.1109/TCAD.2004.826582