Automatic Design Space Exploration of Register Bypasses in Embedded Processors

Register bypassing is a popular and powerful architectural feature to improve processor performance in pipelined processors by eliminating certain data hazards. However, extensive bypassing comes with a significant impact on cycle time, area, and power consumption of the processor. Recent research t...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2007-12, Vol.26 (12), p.2102-2115
Main Authors: Shrivastava, A., Park Sanghyun, Earlie, E., Dutt, N.D., Nicolau, A., Paek Yunheung
Format: Article
Language:English
Subjects:
Bypass
Bypasses
Communication industry
Design
Design engineering
Electronics industry
Energy consumption
Estimates
Exploration
forwarding path
Hazards
Information technology
Logic
Microprocessors
Multidimensional systems
operation table (OT)
partial bypassing
partially bypassed processor
Performance evaluation
pipeline hazard detection
Pipelines
processor pipeline
Registers
Space exploration
Studies
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Summary:Register bypassing is a popular and powerful architectural feature to improve processor performance in pipelined processors by eliminating certain data hazards. However, extensive bypassing comes with a significant impact on cycle time, area, and power consumption of the processor. Recent research therefore advocates the use of partial bypassing in a processor. However, accurate performance evaluation of partially bypassed processors is still a challenge, primarily due to the lack of bypass-sensitive retargetable compilation techniques. No existing partial bypass exploration framework estimates the power and area overhead of partial bypassing. As a result, the designers end up making suboptimal design decisions during the exploration of partial bypass design space. This paper presents PBExplore - an automatic design-space-exploration framework for register bypasses. PBExplore accurately evaluates the performance of a partially bypassed processor using a bypass-sensitive compilation technique. It synthesizes the bypass control logic and estimates the area and energy overhead of each bypass configuration. PBExplore is thus able to effectively perform multidimensional exploration of the partial bypass design space. We present experimental results of benchmarks from the MiBench suite on the Intel XScale architecture on and demonstrate the need, utility, and exploration capabilities of PBExplore.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2007.907066