A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2022-11, Vol.41 (11), p.4575-4586
• Main Authors: Lu, Yi-Chen, Pentapati, Sai, Zhu, Lingjun, Murali, Gauthaman, Samadi, Kambiz, Lim, Sung Kyu
• Format: Article
• Language: English
• Subjects: 3D integrated circuits (ICs); Algorithms; circuit partitioning; Degradation; Design parameters; Graph neural networks; Integrated circuits; Machine learning; Partitioning; Partitioning algorithms; physical design; Routing; Three-dimensional displays; Three-dimensional integrated circuits; Timing; Two dimensional flow
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2021.3139310

Tier partitioning is one of the most critical stages in monolithic 3-D (M3D) integrated circuits (ICs) implementation flows. It transforms 2-D netlists into 3-D by performing tier assignment for each design instance, which directly impacts the power, performance, and area (PPA) metrics of final 3-D full-chip designs. However, the current state-of-the-art tier partitioning approach named bin-based min-cut algorithm has fundamental flaws that lead to severe drawbacks, such as timing degradation, 3-D routing overhead, and redundant monolithic intertier vias (MIVs) insertion. To overcome these issues, in this article, we propose TP-GNN, an unsupervised graph learning-based tier partitioning framework that utilizes graph neural networks (GNNs) and advanced machine learning (ML) techniques to perform tier partitioning. The proposed framework comprehends design- and technology-related parameters properly so that it is generalizable to various netlists and technologies. In addition, it can be integrated with any style of M3D design flows that require tier assignments of standard cells. In the experiments, we validate the proposed framework on seven industrial designs with two different fashions of M3D implementation flows: 1) partitioning-first (Snap3D) and 2) partitioning-last (Shrunk2D and Compact2D) flows. We demonstrate that our framework, TP-GNN, significantly improves the 3-D quality of results (QoR) across most testing designs in a large margin compared with the bin-based min-cut tier partitioning algorithm. Specifically, in OpenPiton, an RISC-V-based multicore system, we observe 27.4%, 7.7%, and 20.3% improvements in performance, wirelength, and energy-per-cycle, respectively. Finally, we perform a case study by applying the proposed framework to a heterogeneous M3D design flow, Pin3D, on a commercial CPU design and observe that TP-GNN reaches better partitioning solutions than the existing partitioning approaches for heterogeneous 3-D ICs.