Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization

A delay-locked loop (DLL) circuit is indispensable for clock synchronization in a chip incorporating several heterogeneous dice. It has been shown previously that a fault and soft-error-tolerant DLL can be achieved by triple-module redundancy (TMR) enhanced with a timing correction scheme. However,...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2023-08, Vol.42 (8), p.2761-2765
Main Authors: Su, Yung-Chuan, Huang, Shi-Yu
Format: Article
Language:English
Subjects:
Circuit faults
Circuits
Clock synchronization
Clocks
Codes
Delay lines
Delay-locked loop (DLL)
Delays
Fault tolerance
fault-tolerant
Field effect transistors
process resilient
Redundancy
soft error
Soft errors
Synchronization
timing correction scheme
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Summary:A delay-locked loop (DLL) circuit is indispensable for clock synchronization in a chip incorporating several heterogeneous dice. It has been shown previously that a fault and soft-error-tolerant DLL can be achieved by triple-module redundancy (TMR) enhanced with a timing correction scheme. However, the prior work still has a severe limitation-it does not consider the latency of the clock tree, and this limitation will make it infeasible in realistic situations. We demonstrate in this article that this limitation can be overcome by a new "clock-latency-aware" architecture, thereby making a fault and soft-error-tolerant DLL truly realistic.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2022.3226156