ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2024-11, Vol.43 (11), p.4178-4189
• Main Authors: Zhao, Xuyang, Gao, Tianning, Zhao, Aidong, Bi, Zhaori, Yan, Changhao, Yang, Fan, Wang, Sheng-Guo, Zhou, Dian, Zeng, Xuan
• Format: Article
• Language: English
• Subjects: Asynchronous parallel optimization; Design optimization; Design parameters; high-dimensional design space exploration (DSE); Input variables; Microarchitecture; Optimization; Parameter sensitivity; Power demand; Program processors; region of interest (ROI); RISC-V microarchitecture; Rockets; Self organizing maps; Self-organizing feature maps; Sensitivity; Space exploration; variable selection (VS); Very large scale integration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2024.3443006

Exploring the design space of RISC-V processors faces significant challenges due to the vastness of the high-dimensional design space and the associated expensive simulation costs. This work proposes a region of interest (ROI)-driven method, which focuses on the promising ROIs to reduce the over-exploration on the huge design space and improve the optimization efficiency. A tree structure based on self-organizing map (SOM) networks is proposed to partition the design space into ROIs. To reduce the high dimensionality of design space, a variable selection technique based on a sensitivity matrix is developed to prune unimportant design parameters and efficiently hit the optimum inside the ROIs. Moreover, an asynchronous parallel strategy is employed to further save the time taken by simulations. Experimental results demonstrate the superiority of our proposed method, achieving improvements of up to 43.82% in performance, 33.20% in power consumption, and 11.41% in area compared to state-of-the-art methods.