Hybrid parallel motion estimation architecture based on fast top-winners search algorithm

• Published in: IEEE transactions on consumer electronics 2010-08, Vol.56 (3), p.1837-1842
• Main Authors: Lai, Yeong-kang, Chen, Lien-fei, Huang, Shien-yu
• Format: Article
• Language: English
• Subjects: Algorithm design and analysis; Algorithms; Architecture; Arrays; Computation; Electronics; Hardware; Memory management; Motion estimation; partial distortion elimination (PDE); pel-subsampling; Pixel; Pixels; Search algorithms; VLSI
• ISSN: 0098-3063; 1558-4127
• DOI: 10.1109/TCE.2010.5606334

In this paper, a hybrid parallel motion estimation architecture based on the fast top-winners algorithm is proposed. In the first instance, the fast top-winners search algorithm is discussed based on the pel-subsampling technique to reduce the computational amount of the sum of absolute difference (SAD). Moreover, the four-parallel spiral scanning (4PSP) with the partial distortion elimination (PDE) mechanism is also utilized to early terminate the unnecessary SAD. Therefore, the proposed fast algorithm can not only avoid trapping into the problem of the local minimum but also save the computational operations with a little performance degradation. According to our proposed algorithm, the 4×4 processing element (PE) array and the dual mode SAD tree are proposed to efficiently perform SAD and Sub-SAD which is accumulated based on the pel-subsampling. For the sake of reducing the system memory bandwidth and decreasing the frequency of the memory access, the local memory configuration and the novel memory interleaving organization are proposed to arrange the current data and reference pixels easily, to access the image pixels efficiently, and to achieve the Level C (Lv. C) data reuse scheme.