Sparse channelizer for FPGA-based simultaneous multichannel DRM30 receiver

The paper describes a channelization architecture that simultaneously extracts all radio stations in the DRM30 standard, that is intended to be an important part of a future receiver to simultaneously demodulate the entire 0 - 30 MHz broadcast band for content and metadata indexing applications. The...

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Bibliographic Details
Published in:IEEE transactions on consumer electronics 2015-05, Vol.61 (2), p.151-159
Main Authors: Tietche, Brunel Happi, Romain, Olivier, Denby, Bruce
Format: Article
Language:English
Subjects:
Bandwidth
Channelization
DRM30
Electronics
Engineering Sciences
Field programmable gate arrays
Filter banks
Filtering algorithms
Finite impulse response filters
FPGA
Frequency modulation
Indexing applications
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Summary:The paper describes a channelization architecture that simultaneously extracts all radio stations in the DRM30 standard, that is intended to be an important part of a future receiver to simultaneously demodulate the entire 0 - 30 MHz broadcast band for content and metadata indexing applications. The system, which contains overlap-add and Goertzel algorithms, is implemented on a single Field- Programmable Gate Array (FPGA), thus offering the possibility of use in real time applications. This novel architecture achieves superior efficiency by minimizing multiplication calculational resources, as compared to existing FPGA-based channelizers. Chip resource utilization details and experimental results from the developed prototype are also presented.
ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2015.7150568