Utilizing Process Variations for Reference Generation in a Flash ADC

This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and low-power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference voltage generation network has been eliminated...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2009-05, Vol.56 (5), p.364-368
Main Authors: Sundstrom, T., Alvandpour, A.
Format: Article
Language:English
Subjects:
Analog-digital conversion
Calibration
Circuits
CMOS
CMOS process
CMOS technology
Comparators
Electric potential
Flash analog-to-digital converter (ADC)
High speed
high-performance design
Nanocomposites
Nanomaterials
Nanostructure
parameter variation
Power dissipation
Redundancy
TECHNOLOGY
TEKNIKVETENSKAP
Threshold voltage
Very large scale integration
Voltage
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Summary:This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and low-power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference voltage generation network has been eliminated in a 4-bit Flash ADC in 90-nm CMOS, with small-sized comparators. The native comparator offsets, resulting from the process-variation-induced mismatch, are used as the only source of reference levels, and redundancy is used to acquire the desired resolution. The measured performance of the 1.5-GS/s ADC is comparable to traditional state-of-the art ADCs and dissipates 23 mW.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2009.2019165