On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits

Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Th...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2010-10, Vol.57 (10), p.798-802, Article 798
Main Authors: Kim, Kyung Ki, Wang, Wei, Choi, Ken
Format: Article
Language:English
Subjects:
Aging
Circuits
Degradation
Devices
Digital circuits
hot carrier injection (HCI)
Human computer interaction
Integrated circuit modeling
Monitoring
MOSFETs
negative bias temperature instability (NBTI)
Niobium base alloys
Performance degradation
Phase shift
reliability
Sensors
Stress
Temperature
Temperature sensors
Threshold voltage
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Summary:Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 x 7.97 μm 2 ; the post-layout power consumption is 18.57 μW during NBTI/HCI stress mode and 30.86 μW during NBTI/HCI measurement mode on average.
ISSN:1549-7747
0098-4094
1558-3791
1558-1276
DOI:10.1109/TCSII.2010.2067810