A Low-Power DCO Using Interlaced Hysteresis Delay Cells

• Published in: IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2012-10, Vol.59 (10), p.673-677
• Main Authors: Yu, Chien-Ying, Chung, Ching-Che, Yu, Chia-Jung, Lee, Chen-Yi
• Format: Article
• Language: English
• Subjects: All-digital phase-locked loop (ADPLL); Clocks; Computer architecture; Delay; digitally controlled oscillator (DCO); interlaced hysteresis delay cell (IHDC); Logic gates; low power; Phase locked loops; Power demand; Transistors
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2012.2213357

This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-fine architecture with binary-weighted delay stages is applied for the delay range and resolution optimization. The coarse-tuning stage of the DCO uses the interlaced hysteresis delay cell, which is power and area efficient, as compared with conventional delay cells. The glitch protection synchronous circuit makes the DCO easily controllable without generating glitches. A demonstrative all-digital phase-locked loop using the DCO is fabricated in a 90-nm CMOS process with an active area of 0.0086 mm 2 . The measured output frequency range is 180-530 MHz at the supply of 1 V. The power consumption are 466 and 357 μW at 480- and 200-MHz output, respectively.