Static Differential NCL Gates: Toward Low Power

This brief proposes a new topology for implementing differential null convention logic gates. The new topology relies on the static implementation of conventional versions of such gates and uses a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes whil...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2015-06, Vol.62 (6), p.563-567
Main Authors: Moreira, Matheus Trevisan, Arendt, Michel, Moraes, Fernando Gehm, Calazans, Ney Laert Vilar
Format: Article
Language:English
Subjects:
asynchronous circuits
Circuits and systems
Delay
differential logic
Dynamics
Electric power generation
Gates
High strength steels
low power
null convention logic
quasi-delay-insensitive circuits
Semiconductor devices
Topology
Transistors
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Summary:This brief proposes a new topology for implementing differential null convention logic gates. The new topology relies on the static implementation of conventional versions of such gates and uses a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes while the gate is switching. It shows that albeit the extra transistors adding cost in area, they enable solid savings in dynamic and static power and improve transition delays. Electrical simulation results for a Kogge-Stone adder case study led to savings of 67.3% in dynamic power, 61.9% in static power, 67.2% in energy per operation, and 8.9% in forward propagation delay, when compared with a state-of-the-art differential topology.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2015.2407198