Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit

This brief proposes a dynamic error-compensation circuit for a fixed-width squarer based on the Booth-folding technique. According to the expected value of the partial product through the Booth encoder, a closed form of the compensated value can be derived, including column information that can be u...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2015-09, Vol.62 (9), p.851-855
Main Author: Chen, Yuan-Ho
Format: Article
Language:English
Subjects:
Accuracy
Arrays
Booth folding technique
Circuits
Circuits and systems
CMOS
Delays
dynamic error-compensation
Dynamical systems
Dynamics
Encoders
Finite wordlength effects
Fixed-width squarer
Mathematical analysis
Mathematical models
probability theory
Semiconductors
Signal to noise ratio
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Summary:This brief proposes a dynamic error-compensation circuit for a fixed-width squarer based on the Booth-folding technique. According to the expected value of the partial product through the Booth encoder, a closed form of the compensated value can be derived, including column information that can be used to improve accuracy. The proposed compensation circuit was derived using a mathematical probability model, which means that it is easily implemented for bit lengths of 32, 64, and longer. Implemented using the Taiwan Semiconductor Manufacturing Company Ltd. 0.18- μm CMOS process, the proposed 32-bit squarer achieved an operation frequency of 50 MHz and a gate count of 3.7 k. Compared with previous solutions, the proposed squarer achieves the best tradeoff between area efficiency, cost, and accuracy.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2015.2435752