Twenty Years of Near/Sub-Threshold Design Trends and Enablement

This brief surveys the past 20 years of near/sub-threshold digital integrated circuit design. Most of the chips have been highly characterized for voltage scaling down to near/sub-threshold, and a significantly custom design effort has been reported to achieve reliable operation. In this brief, we a...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2021-01, Vol.68 (1), p.5-11
Main Authors: Singh, Kamlesh, Pineda de Gyvez, Jose
Format: Article
Language:English
Subjects:
Body-biasing
Circuit design
Custom design
Delays
Design standards
Electric potential
Electric power
Electricity generation
Foundries
Integrated circuits
Libraries
near/sub-threshold
power delivery
process variation
pruning
Random access memory
standard cell library
Transistors
ultra-low power
ultra-low voltage
Voltage
Voltage control
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Summary:This brief surveys the past 20 years of near/sub-threshold digital integrated circuit design. Most of the chips have been highly characterized for voltage scaling down to near/sub-threshold, and a significantly custom design effort has been reported to achieve reliable operation. In this brief, we address the challenges of process variations and discuss the circuits and methods used over the years to minimize this impact. We discuss the advantages of standard-cell library design and provide a more involved pruning method to improve performance and robustness. Finally, we discuss the developments of the usually ignored power delivery techniques for near/sub-threshold circuits. We motivate the use of voltage stacking as a new power delivery technique for near/sub-threshold. This brief provides the basic enablement approaches for designing a chip operating in the near/sub-threshold region based on our experience.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2020.3040970