A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier

A pipelined SAR ADC is proposed to achieve faster conversion by employing residue conversion and partial bit conversion in parallel to lessen timing constraints. Additionally, a varactor-based dynamic amplifier is adopted to improve linearity for a 10-b accuracy. The single-channel ADC achieves 1 GS...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2022-04, Vol.69 (4), p.2021-2025
Main Authors: Chang, Hao-Hsuan, Lin, Tung-Cheng, Lee, Tai-Cheng
Format: Article
Language:English
Subjects:
Amplifiers
Analog-digital conversion
Capacitance
Conversion
dynamic amplifier
Linearity
parallel conversion
Pipelined SAR ADC
Registers
Residues
single channel
Switches
Varactor diodes
varactor-based compensation
Varactors
Voltage
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Summary:A pipelined SAR ADC is proposed to achieve faster conversion by employing residue conversion and partial bit conversion in parallel to lessen timing constraints. Additionally, a varactor-based dynamic amplifier is adopted to improve linearity for a 10-b accuracy. The single-channel ADC achieves 1 GS/s with a peak SNDR 41.37 dB at a Nyquist input and consumes 9.4 mW.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2022.3142099