A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC

• Published in: IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2023-02, Vol.70 (2), p.1-1
• Main Authors: Kim, Ho-Jin, Boo, Jun-Ho, Cho, Kang-Il, Kwak, Yong-Sik, Ahn, Gil-Cho
• Format: Article
• Language: English
• Subjects: Analog to digital converters; analog-to-digital converter (ADC); Bandwidth; Clocks; data weighted averaging; Delta-sigma (ΔΣ); Digital to analog converters; Gain; Integrators; Multi-stage noise shaping; Noise levels; open-loop integrator; Power consumption; Quantization (signal); reference shuffling; source follower; switched-capacitor circuits; Topology; Transfer functions; Voltage
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2022.3212147

This paper presents a single-loop third-order discrete-time delta-sigma (ΔΣ) analog-to-digital converter (ADC). The proposed ΔΣ ADC employs source-follower (SF)-based open-loop switched-capacitor (SC) integrators to achieve high-speed operation with efficient power consumption. A modified feed-forward topology is proposed to improve the linearity of the modulator using the SF-based integrators. An interpolating 4-bit flash quantizer with an embedded data weighted averaging (DWA) function is employed to address the nonlinearity of the feedback digital-to-analog converter (DAC) for high speed operation. The prototype ADC implemented in a 65nm CMOS technology achieves 75.4-dB dynamic range (DR) and 73.3-dB peak signal-to-noise-and-distortion ratio (SNDR) over 10-MHz bandwidth with an oversampling ratio (OSR) of 16. The power consumption of the modulator is 13.3-mW from a 1.1-V supply, resulting in the Walden and Schreier figure-of-merits (FoMW and FoMS) of 174-fJ/conversion-step and 164-dB, respectively.