Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory

As the physical size of dynamic random-access memory (DRAM) technology continues to decrease, the effects of process fluctuations on the transistor-threshold voltage are becoming increasingly serious. The offset voltage as a key parameter of the core circuit, is caused by the mismatch of the transis...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2024-04, Vol.71 (4), p.1759-1763
Main Authors: Liu, Li, Tai, Dele, Qiang, Bin, Guan, Lijun, Peng, Chunyu, Dai, Chenghu, Hao, Licai, Lu, Wenjuan, Lin, Zhiting, Zhao, Qiang, Wu, Xiulong
Format: Article
Language:English
Subjects:
Calibration
Capacitance
Compensation
DRAM
Dynamic random access memory
Inverters
ISO
Line voltage
Mismatch (electrical)
offset-compensation
Random access memory
Self calibration
sense amplifier
Sense amplifiers
Sensors
Threshold voltage
Transistors
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Summary:As the physical size of dynamic random-access memory (DRAM) technology continues to decrease, the effects of process fluctuations on the transistor-threshold voltage are becoming increasingly serious. The offset voltage as a key parameter of the core circuit, is caused by the mismatch of the transistor threshold voltage in the sense-amplifier (SA) and it significantly affects the accuracy of data read from DRAM. Therefore, this brief analyzes the timings, working processes, and simulations of three SA circuits, the offset cancellation sense amplifier (OCSA), boosted reference voltage sense amplifier (BRVSA), and offset mismatch calibration sense amplifier (OMCSA). Subsequently, a novel flip point offset-compensation sense amplifier (FPOCSA) is proposed. An offset voltage storage cell is formed during the self-calibration phase owing to the offset-compensation effect of the flip point. Moreover, the bit-line voltage difference is amplified to improve the sensing margin and robustness. According to the post-layout simulation results under 65nm CMOS technology, the standard deviation of the FPOCSA offset voltage is 3.50 mV, which is 70.6%, 47.6%, and 21.2% lower than OCSA, BRVSA, and OMCSA, respectively.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2023.3329198