Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network

This brief uses the capacitive charge coupling method to present a multi-bit SRAM-based compute-in-memory (CIM) architecture in the analog domain. The proposed architecture consists of a 64\times 64\,\,9 T1C SRAM array performing 1024 MAC operations between input activation (4-bit) and weight (4-bi...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2024-06, Vol.71 (6), p.3166-3170
Main Authors: Kushwaha, Dinesh, Abotula, Jaya Kumar, Kohli, Rajat, Mishra, Jwalant, Dasgupta, Sudeb, Bulusu, Anand
Format: Article
Language:English
Subjects:
accuracy
Analog
bitline
capacitor
Capacitors
Common Information Model (computing)
compute in-memory (CIM)
Computer architecture
Couplings
energy
Logic gates
multi-bit
Random access memory
Static random access memory
Transistors
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This brief uses the capacitive charge coupling method to present a multi-bit SRAM-based compute-in-memory (CIM) architecture in the analog domain. The proposed architecture consists of a 64\times 64\,\,9 T1C SRAM array performing 1024 MAC operations between input activation (4-bit) and weight (4-bit) in a cycle, and an optimized 4-bit Flash ADC is used for converting the analog MAC into digital output. This brief achieves a throughput of 455 GOPS and an energy efficiency of 1012 TOPS/W at 222 MHz, maintaining a very high signal margin of 54 mV. The achieved inference accuracy is 98% for MNIST and 86% for the CIFAR-10 data set. This proposed work is implemented on a 28 nm CMOS Technology node at 0.9 V supply.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2023.3329261