Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2009-07, Vol.56 (7), p.1428-1441
• Main Authors: Myeong-Eun Hwang, Seong-Ook Jung, Roy, K.
• Format: Article
• Language: English
• Subjects: Benchmark testing; Circuit simulation; Circuit testing; Circuits; CMOS logic; CMOS technology; Computer simulation; Delay; Delay estimation; Driver circuits; Drivers; Dynamics; gate delay; Gates (circuits); Integrated circuit interconnections; interconnect delay; logical effort; Mathematical analysis; Mathematical models; Semiconductor device modeling; Signal analysis; signal slope; Studies; Wire
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2008.2006217

We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of < 5.3% at each stage and < 4.3% for the path delay with a speedup of three orders of magnitude over HSPICE at the 130-nm technology node. Two test chips have been fabricated in 90- and 65-nm CMOS technologies to verify the effectiveness of the proposed model. Measured results show that, for a wide range of interconnect lengths (2000 and 1400 mum ) and geometries, the proposed model predicts the circuit delay with an error of 5.7% at a supply voltage of V dd =1.2 V and 4.8% at V dd =0.3 V .