A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Pro...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-04, Vol.55 (3), p.796-803
Main Authors: Rennie, D., Sachdev, M.
Format: Article
Language:English
Subjects:
Calibration
CDR circuits
Circuits
clock and data recovery (CDR)
Clocks
CMOS
CMOS circuits
Detectors
Frequency
Linear phase
Offsets
Phase detection
Pseudorandom
ring oscillator
Robustness
Semiconductor device measurement
Silicon
Voltage-controlled oscillators
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Summary:This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting the circuits in a way which is difficult to design for, making calibration an attractive solution. Both the calibration algorithm and test chip implementation are described and measured results are presented. The CDR circuit was fabricated in a 0.18-mum, six metal layer standard CMOS process. With a pseudorandom bit sequence of 2 7 - 1 calibration improved the measured bit error rate from 4.6 x 10 -2 to less than 10 -13 .
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.916400