Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2012-02, Vol.59 (2), p.276-284
• Main Authors: Lingli Xia, Jingguang Wang, Beattie, W., Postman, J., Chiang, P. Y.
• Format: Article
• Language: English
• Subjects: Calibration; Clocks; Delay; Detectors; Histogram counter; Measurement uncertainty; multi-phase; Phase measurement; time-interleaved; timing error calibration
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2011.2162382

A foreground digital calibration method is presented that calibrates the timing offsets between the multiple T/H (track/hold) circuits of time-interleaved analog-to-digital converters and multi-phase serial links. Two quantizer-based phase detectors sample the outputs of adjacent track/hold circuits, detecting any phase offsets arising from process mismatches in both the timing verniers and the T/H switches, and store the resulting digital decisions in histogram counters. Measurement inaccuracies resulting from quantizer offset are averaged away statistically by a round-robin rotation of the dual samplers, compensating for comparator imprecision. Built in a 90-nm CMOS process, the proposed calibration technique, after three iterations of both the phase measurement and subsequent timing vernier adjustment, reduces the static phase offset of each channel to less than ±0.5 ps in an 8-channel, 8 GS/s time-interleaved system. Further measurements using a T/H circuit as a down-conversion mixer confirm a residual phase error of less than ±2 ps.