Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2013-03, Vol.60 (3), p.517-528
Main Authors: Nagaraj, K., Kamath, A. S., Subburaj, K., Chattopadhyay, B., Nayak, G., Evani, S., Nayak, N. P., Prathapan, I., Zhang, F., Haroun, B.
Format: Article
Language:English
Subjects:
Bandwidth
Circuits
Clocks
Construction
Digital
Digital phase lock loops
Dividers
Locks
Modular
Oscillators
Phase error
phase lock loops
Phase locked loops
Phase noise
Ring oscillators
Temperature distribution
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Summary:This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2013.2246311