A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN

A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets WiGig standard requirements with only background offset and gain calibrations. Skew tolerance is achieved by using a "correct-by...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2015-08, Vol.62 (8), p.1929-1939
Main Authors: Kundu, Sandipan, Alpman, Erkan, Lu, Julia Hsin-Lin, Lakdawala, Hasnain, Paramesh, Jeyanandh, Byunghoo Jung, Zur, Sarit, Gordon, Eshel
Format: Article
Language:English
Subjects:
ADCs
Bandwidth
Calibration
Capacitors
Clocks
Receivers
SAR
semi-synchronous
skew-tolerant
Switches
switching-energy
time-interleaving
Timing
WiGig
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Summary:A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets WiGig standard requirements with only background offset and gain calibrations. Skew tolerance is achieved by using a "correct-by-construction," timing-calibration-free global bottom-plate sampling scheme. The ADC achieves a sampling rate of 2.64 GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40 nm LP CMOS design dissipates 39 mW from 1.2 V. The TI-SAR ADC characterized with an integrated receiver front-end achieves -21.44 dB EVM at sensitivity with a QAM16 signal.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2015.2452372