A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design

This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic power consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist techniq...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2016-08, Vol.63 (8), p.1164-1175
Main Authors: Choi, Woong, Park, Jongsun
Format: Article
Language:English
Subjects:
Assist
capacitive coupling
charge-recycling
Circuits
Design engineering
Dynamical systems
Dynamics
Electric potential
FinFETs
Power consumption
Power demand
Random access memory
read stability
Reliability engineering
SRAM
Stability analysis
Static random access memory
variation
Voltage
write ability
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Summary:This paper presents a novel charge-recycling SRAM assist circuit to reduce the dynamic power consumption of SRAM assist technique. By collaboratively combining the read and write assist schemes, the wasted charge in conventional read assist circuit can be efficiently recycled in write assist technique. In order to compare the dynamic power consumption at ISO minimum operating voltage (V MIN ) condition, the most probable failure point (MPFP) simulations are performed using 14 nm FinFET technology model. Compared to the conventional assist schemes, thanks to the charge-recycling, 41% power saving, and 2.3% area reduction can be achieved by using the proposed SRAM assist circuit.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2016.2589118