A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization

A capacitive DAC is an important building block of a charge-redistribution SAR ADC, for its size has a significant impact on performance. For medium- to high-resolution applications, the size of the DAC is typically determined by random mismatches. As such, an effective mismatch calibration circuit...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2020-09, Vol.67 (9), p.2883-2896
Main Authors: Bagheri, Mojtaba, Schembari, Filippo, Pourmousavian, Naser, Zare-Hoseini, Hashem, Hasko, David, Staszewski, Robert Bogdan
Format: Article
Language:English
Subjects:
Analog-digital conversion
Calibration
capacitive DAC
Capacitors
Circuits
CMOS
CMOS technology
Gaussian process
Linearity
Measurement
mismatch calibration
Power efficiency
Prototypes
Quantization (signal)
SAR analog-to-digital converter (ADC)
Self calibration
stochastic
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Summary:A capacitive DAC is an important building block of a charge-redistribution SAR ADC, for its size has a significant impact on performance. For medium- to high-resolution applications, the size of the DAC is typically determined by random mismatches. As such, an effective mismatch calibration circuit can allow the DAC to be scaled down to a much lower kT/C noise limit, thereby increasing the overall ADC power efficiency. This paper reviews some of the most important reported mismatch calibration techniques and proposes a foreground calibration method based on a deterministic self-calibration and stochastic quantization. This approach is experimentally validated on a prototype 10-bit SAR ADC fabricated in TSMC 28-nm LP CMOS technology, demonstrating an INL and SFDR improvement of respectively 6.4 LSB and 14.9 dB at 85 MS/s.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2020.2985816