A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2022-05, Vol.69 (5), p.1990-2001
• Main Authors: Ding, Chen, Huan, Yuxiang, Jia, Hao, Yan, Yulong, Yang, Fanxi, Liu, Lizheng, Shen, Meigen, Zou, Zhuo, Zheng, Lirong
• Format: Article
• Language: English
• Subjects: address event representation; cache-like spike weight indexing; Chip formation; Data communication; Data models; Field programmable gate arrays; Flow control; general unicast flow control; hybrid-mode router; load-aware multicast routing algorithm; Multi-chip network; multicast; Multicasting; Neuromorphic computing; Neuromorphics; Neurons; Routing; spiking neural network; System-on-chip; Unicast
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2022.3145016

Large-scale neuromorphic computing requires the multi-chip network to provide high computing power. Efficient routing schemes and on-chip router design are necessary for handling various inter-chip transmission patterns. In this paper, we propose a hybrid-mode on-chip router that supports both multicast and unicast routing for the large-scale neuromorphic simulation. Two routing schemes, namely Cache-like Spike Weight Indexing and General Unicast Flow Control, are proposed to accommodate the chip-to-chip transmission of spike and non-spike data. This work is evaluated on a neuromorphic platform built with an 8\times 8 FPGA chips array. Running a simulation of 1M neurons at 200MHz, the proposed router achieves a processing latency of 25ns and a chip-to-chip latency of 287ns. Working in the unicast mode, the router can synchronize status flags of all chips within 5 ~\mu \text{s} . Moreover, it reduces the peak spike traffic by 25.65% with the help of Load-aware Multicast Routing, compared with other multicast routing strategies.