Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2022-12, Vol.69 (12), p.1-10
• Main Authors: Fu, Yarong, Wang, Wang, Zhong, Xin, Li, Manni, Li, Zixu, Dong, Qing, Jiang, Yu, Lin, Yinyin
• Format: Article
• Language: English
• Subjects: aging; Defects; Degradation; Layout; Monitoring; NBTI; Negative bias temperature instability; Recovery; SRAM; Static random access memory; statistical; Testing; Thermal variables control
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2022.3206448

An on-chip digital sensor has been demonstrated in 28nm High-k Metal Gate (HKMG) for bias temperature instability (BTI) statistical characterization with the benefits: fast statistical measurement, less recovery impact (Toff-stress@around 15ns, Fast Period Sampling (FPS) @around 300ns), and high resolution (0.1mV of \Delta Vth). As far as we know, it is the first time to statistically observe the very early stage of trap recovery of individual device in practical scenario, e.g., static random-access memory (SRAM). We find that three Negative BTI (NBTI) recovery behaviors, 2/3/4-step with clear transition slope, co-exist in HKMG devices. Our further analysis ascribes the phenomena to co-existing of four types of defects in 28nm HKMG Devices Under Test (DUTs). Three types are recoverable and one unrecoverable. The transition slope instead of steep drop between steps is the aggregative effects of one certain type of recoverable defect contained across DUTs. More types of defects lead to more Vth shift. But the contribution percentage of unrecoverable defect remains quite close, while recoverable defects dominate the Vth degradation. Only when the Toff-stress is less than the starting point of 1st recover step (within 1 \mu s in our case), accurate and consistent Vth degradation data can be achieved.