A Novel Neuromorphic Hardware Using Area-Efficient Chain RRAM-Based Synapses and Compact Neurons With (Anti-) Integration Scheme

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2024-09, p.1-14
• Main Authors: Wu, Qiqiao, Yang, Honghu, Liu, Yixuan, Cao, Yue, Han, Yongkang, Jiang, Haijun, Zhou, Keji, Yi, Hailan, Yang, Jianguo, Liu, Qi
• Format: Article
• Language: English
• Subjects: chain structure; Costs; Firing; Hardware; Membrane potentials; memory lifetime; neural network; neuromorphic hardware; Neuromorphics; Neurons; Resistive random-access memory (RRAM); Transistors
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2024.3458436

The neuromorphic system aims to implement large-scale spiking neural networks (SNN) through hardware, ultimately achieving human-level intelligence. At this stage, it is difficult for a single silicon-based chip to reach the density of the human brain, so it is important to improve the area efficiency of neuromorphic chips. We present a novel neuromorphic hardware that employs high area-efficiency chain RRAM synaptic array, and compact RRAM-based neurons. The proposed chain RRAM structure achieves a small cell size of 41.5F ^{2} at 28 nm logic process. Compared to the conventional 1T1R structure, the chain structure has a 22.2% area reduction and a 58.8% parasitic capacitance reduction. As for the neuron design, we use RRAM instead of the capacitor to integrate membrane voltage. To alleviate the endurance issue of RRAM, we propose an (anti-) integration scheme that removes the operation of membrane voltage reset. The simulation results demonstrate an average energy consumption of 1.15pJ per spike and an area of 15.9 \mu m ^{2} . With the (anti-)integration scheme, the RRAM's lifetime is demonstrated to extend by 2 \times and the energy of programming RRAM is demonstrated to be reduced by 2 \times .