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A "2 + 1" Cores Triple-Mode Oscillator
This paper proposes a millimeter-wave (mmW) oscillator with "2 + 1" cores and triple operation modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a negative transconductance cell, is introduced to the regular dual-core oscillator to generate a third mode wi...
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Published in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2024-10, p.1-14 |
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creator | Deng, Shuai Yi, Xiang Qin, Pei Xu, Taotao Wan, Cao Luo, Xiongyao Che, Wenquan Xue, Quan |
description | This paper proposes a millimeter-wave (mmW) oscillator with "2 + 1" cores and triple operation modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a negative transconductance cell, is introduced to the regular dual-core oscillator to generate a third mode with enhanced effective Q . This auxiliary core not only broadens the tuning range without compromising phase noise or chip area but also avoids the risk of introducing mismatch into two regular cores like triple-core oscillators. The demand for low interconnect resistance is relieved because of the merits of less core mismatch and extra magnetic injection lock path. The behavior of the proposed oscillator in different modes is studied analytically. A quantitative analysis of phase noise and interconnect resistance in the dual-core oscillator is presented and verified against circuit simulations. Implemented in a 65-nm CMOS process, the oscillator achieves a 72.24% tuning range from 16.35 to 35.48 GHz and a peak figure-of-merit of tuning range and area (FoM _{\mathrm{TA}}) of -217.07 dBc/Hz at 20.27 GHz with 1 MHz frequency offset. The chip operates from a 1 V supply with a power consumption from 6.3 to 21.76 mW and a core area of 0.075 mm ^{2} . |
doi_str_mv | 10.1109/TCSI.2024.3473689 |
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An auxiliary core, comprising a switch and a negative transconductance cell, is introduced to the regular dual-core oscillator to generate a third mode with enhanced effective <inline-formula> <tex-math notation="LaTeX">Q</tex-math> </inline-formula>. This auxiliary core not only broadens the tuning range without compromising phase noise or chip area but also avoids the risk of introducing mismatch into two regular cores like triple-core oscillators. The demand for low interconnect resistance is relieved because of the merits of less core mismatch and extra magnetic injection lock path. The behavior of the proposed oscillator in different modes is studied analytically. A quantitative analysis of phase noise and interconnect resistance in the dual-core oscillator is presented and verified against circuit simulations. Implemented in a 65-nm CMOS process, the oscillator achieves a 72.24% tuning range from 16.35 to 35.48 GHz and a peak figure-of-merit of tuning range and area (FoM<inline-formula> <tex-math notation="LaTeX">_{\mathrm{TA}})</tex-math> </inline-formula> of -217.07 dBc/Hz at 20.27 GHz with 1 MHz frequency offset. The chip operates from a 1 V supply with a power consumption from 6.3 to 21.76 mW and a core area of 0.075 mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula>.]]></description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2024.3473689</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS ; coupled oscillators ; Couplings ; Inductors ; Magnetic cores ; magnetic coupling ; Magnetic resonance ; Millimeter wave technology ; mode switching ; multi-core ; multi-mode ; octave tuning ; Oscillators ; Phase noise ; phase noise (PN) ; Switches ; Tuning ; Voltage-controlled oscillators ; wideband tuning range (TR)</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2024-10, p.1-14</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>eexutt@163.com ; eedengshuai_2019@mail.scut.edu.cn ; eeqxue@scut.edu.cn ; wanc415@foxmail.com ; yixiang@scut.edu.cn ; eewqche@scut.edu.cn ; eeluoxyuuz@mail.scut.edu.cn ; qinpei7777@scut.edu.cn</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10718325$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27923,27924,54795</link.rule.ids></links><search><creatorcontrib>Deng, Shuai</creatorcontrib><creatorcontrib>Yi, Xiang</creatorcontrib><creatorcontrib>Qin, Pei</creatorcontrib><creatorcontrib>Xu, Taotao</creatorcontrib><creatorcontrib>Wan, Cao</creatorcontrib><creatorcontrib>Luo, Xiongyao</creatorcontrib><creatorcontrib>Che, Wenquan</creatorcontrib><creatorcontrib>Xue, Quan</creatorcontrib><title>A "2 + 1" Cores Triple-Mode Oscillator</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description><![CDATA[This paper proposes a millimeter-wave (mmW) oscillator with "2<inline-formula> <tex-math notation="LaTeX">+</tex-math> </inline-formula>1" cores and triple operation modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a negative transconductance cell, is introduced to the regular dual-core oscillator to generate a third mode with enhanced effective <inline-formula> <tex-math notation="LaTeX">Q</tex-math> </inline-formula>. This auxiliary core not only broadens the tuning range without compromising phase noise or chip area but also avoids the risk of introducing mismatch into two regular cores like triple-core oscillators. The demand for low interconnect resistance is relieved because of the merits of less core mismatch and extra magnetic injection lock path. The behavior of the proposed oscillator in different modes is studied analytically. A quantitative analysis of phase noise and interconnect resistance in the dual-core oscillator is presented and verified against circuit simulations. Implemented in a 65-nm CMOS process, the oscillator achieves a 72.24% tuning range from 16.35 to 35.48 GHz and a peak figure-of-merit of tuning range and area (FoM<inline-formula> <tex-math notation="LaTeX">_{\mathrm{TA}})</tex-math> </inline-formula> of -217.07 dBc/Hz at 20.27 GHz with 1 MHz frequency offset. The chip operates from a 1 V supply with a power consumption from 6.3 to 21.76 mW and a core area of 0.075 mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula>.]]></description><subject>CMOS</subject><subject>coupled oscillators</subject><subject>Couplings</subject><subject>Inductors</subject><subject>Magnetic cores</subject><subject>magnetic coupling</subject><subject>Magnetic resonance</subject><subject>Millimeter wave technology</subject><subject>mode switching</subject><subject>multi-core</subject><subject>multi-mode</subject><subject>octave tuning</subject><subject>Oscillators</subject><subject>Phase noise</subject><subject>phase noise (PN)</subject><subject>Switches</subject><subject>Tuning</subject><subject>Voltage-controlled oscillators</subject><subject>wideband tuning range (TR)</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><recordid>eNpNz0tLAzEUBeAgCtbqDxBchC7cyIy5eWdZBh-FSheO6zCZ3MDIyJSkG_-9HdqFq3sW9xz4CLkHVgMw99w2n5uaMy5rIY3Q1l2QBShlK2aZvpyzdJUV3F6Tm1K-GeOOCViQxzVdcfpEYUWbKWOhbR72I1YfU0S6K_0wjt1hyrfkKnVjwbvzXZKv15e2ea-2u7dNs95WPUh7qAy30KMy0fWxc0pHm7RErZRkaFKwoIVKyakARoWkkEcTUHc6hMg6CVIsCZx2-zyVkjH5fR5-uvzrgfkZ6meon6H-DD12Hk6dARH__Rs4epX4A6o-TIM</recordid><startdate>20241015</startdate><enddate>20241015</enddate><creator>Deng, Shuai</creator><creator>Yi, Xiang</creator><creator>Qin, Pei</creator><creator>Xu, Taotao</creator><creator>Wan, Cao</creator><creator>Luo, Xiongyao</creator><creator>Che, Wenquan</creator><creator>Xue, Quan</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/eexutt@163.com</orcidid><orcidid>https://orcid.org/eedengshuai_2019@mail.scut.edu.cn</orcidid><orcidid>https://orcid.org/eeqxue@scut.edu.cn</orcidid><orcidid>https://orcid.org/wanc415@foxmail.com</orcidid><orcidid>https://orcid.org/yixiang@scut.edu.cn</orcidid><orcidid>https://orcid.org/eewqche@scut.edu.cn</orcidid><orcidid>https://orcid.org/eeluoxyuuz@mail.scut.edu.cn</orcidid><orcidid>https://orcid.org/qinpei7777@scut.edu.cn</orcidid></search><sort><creationdate>20241015</creationdate><title>A "2 + 1" Cores Triple-Mode Oscillator</title><author>Deng, Shuai ; Yi, Xiang ; Qin, Pei ; Xu, Taotao ; Wan, Cao ; Luo, Xiongyao ; Che, Wenquan ; Xue, Quan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c148t-7281ce57d9cda956d8f64e65540e7fb81635ff95b175bf5e2d7be6a6bbd0a4143</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CMOS</topic><topic>coupled oscillators</topic><topic>Couplings</topic><topic>Inductors</topic><topic>Magnetic cores</topic><topic>magnetic coupling</topic><topic>Magnetic resonance</topic><topic>Millimeter wave technology</topic><topic>mode switching</topic><topic>multi-core</topic><topic>multi-mode</topic><topic>octave tuning</topic><topic>Oscillators</topic><topic>Phase noise</topic><topic>phase noise (PN)</topic><topic>Switches</topic><topic>Tuning</topic><topic>Voltage-controlled oscillators</topic><topic>wideband tuning range (TR)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Deng, Shuai</creatorcontrib><creatorcontrib>Yi, Xiang</creatorcontrib><creatorcontrib>Qin, Pei</creatorcontrib><creatorcontrib>Xu, Taotao</creatorcontrib><creatorcontrib>Wan, Cao</creatorcontrib><creatorcontrib>Luo, Xiongyao</creatorcontrib><creatorcontrib>Che, Wenquan</creatorcontrib><creatorcontrib>Xue, Quan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Deng, Shuai</au><au>Yi, Xiang</au><au>Qin, Pei</au><au>Xu, Taotao</au><au>Wan, Cao</au><au>Luo, Xiongyao</au><au>Che, Wenquan</au><au>Xue, Quan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A "2 + 1" Cores Triple-Mode Oscillator</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2024-10-15</date><risdate>2024</risdate><spage>1</spage><epage>14</epage><pages>1-14</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract><![CDATA[This paper proposes a millimeter-wave (mmW) oscillator with "2<inline-formula> <tex-math notation="LaTeX">+</tex-math> </inline-formula>1" cores and triple operation modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a negative transconductance cell, is introduced to the regular dual-core oscillator to generate a third mode with enhanced effective <inline-formula> <tex-math notation="LaTeX">Q</tex-math> </inline-formula>. This auxiliary core not only broadens the tuning range without compromising phase noise or chip area but also avoids the risk of introducing mismatch into two regular cores like triple-core oscillators. The demand for low interconnect resistance is relieved because of the merits of less core mismatch and extra magnetic injection lock path. The behavior of the proposed oscillator in different modes is studied analytically. A quantitative analysis of phase noise and interconnect resistance in the dual-core oscillator is presented and verified against circuit simulations. Implemented in a 65-nm CMOS process, the oscillator achieves a 72.24% tuning range from 16.35 to 35.48 GHz and a peak figure-of-merit of tuning range and area (FoM<inline-formula> <tex-math notation="LaTeX">_{\mathrm{TA}})</tex-math> </inline-formula> of -217.07 dBc/Hz at 20.27 GHz with 1 MHz frequency offset. The chip operates from a 1 V supply with a power consumption from 6.3 to 21.76 mW and a core area of 0.075 mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula>.]]></abstract><pub>IEEE</pub><doi>10.1109/TCSI.2024.3473689</doi><tpages>14</tpages><orcidid>https://orcid.org/eexutt@163.com</orcidid><orcidid>https://orcid.org/eedengshuai_2019@mail.scut.edu.cn</orcidid><orcidid>https://orcid.org/eeqxue@scut.edu.cn</orcidid><orcidid>https://orcid.org/wanc415@foxmail.com</orcidid><orcidid>https://orcid.org/yixiang@scut.edu.cn</orcidid><orcidid>https://orcid.org/eewqche@scut.edu.cn</orcidid><orcidid>https://orcid.org/eeluoxyuuz@mail.scut.edu.cn</orcidid><orcidid>https://orcid.org/qinpei7777@scut.edu.cn</orcidid></addata></record> |
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subjects | CMOS coupled oscillators Couplings Inductors Magnetic cores magnetic coupling Magnetic resonance Millimeter wave technology mode switching multi-core multi-mode octave tuning Oscillators Phase noise phase noise (PN) Switches Tuning Voltage-controlled oscillators wideband tuning range (TR) |
title | A "2 + 1" Cores Triple-Mode Oscillator |
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