Microshift: An Efficient Image Compression Algorithm for Hardware

In this paper, we propose a lossy image compression algorithm called microshift. We employ an algorithm-hardware co-design methodology, yielding a hardware-friendly compression approach with low power consumption. In our method, the image is first micro-shifted, and then the sub-quantized values are...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology 2019-11, Vol.29 (11), p.3430-3443
Main Authors: Zhang, Bo, Sander, Pedro V., Tsui, Chi-Ying, Bermak, Amine
Format: Article
Language:English
Subjects:
Algorithms
Co-design
Complexity theory
Compression algorithms
FPGA implementation
Hardware
Image coding
Image compression
Image quality
image sensor
Microshift
MRF model
on-chip image compression
Power consumption
Power efficiency
Quantization (signal)
Signal to noise ratio
Uncertainty
Wireless networks
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Summary:In this paper, we propose a lossy image compression algorithm called microshift. We employ an algorithm-hardware co-design methodology, yielding a hardware-friendly compression approach with low power consumption. In our method, the image is first micro-shifted, and then the sub-quantized values are further compressed. Two methods, FAST and MRF models, are proposed to recover the bitdepth by exploiting the spatial correlation of natural images. Both methods can decompress images progressively. On an average, our compression algorithm can compress images to 1.25-bits per pixel with a resulting quality that outperforms the state-of-the-art on-chip compression algorithms in both peak signal-to-noise ratio and structural similarity. Then, we propose a hardware architecture and implement the algorithm on an FPGA. The results on the ASIC design further validate the low-hardware complexity and high-power efficiency, showing that our method is promising, particularly for low-power wireless vision sensor networks.
ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2018.2880227