Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices

• Published in: IEEE transactions on computers 2007-05, Vol.56 (5), p.673-680
• Main Authors: Ahmadinia, A., Bobda, C., Fekete, S.P., Teich, J., van der Veen, J.C.
• Format: Article
• Language: English
• Subjects: Algorithms; Complexity theory; Computation; Computational geometry; Devices; Field programmable gate arrays; field-programmable gate array (FPGA); free-space manager; geometric optimization; Hardware; line-sweep technique; lower bounds; Maintenance; module placement; Modules; optimal runtime; Optimization; Placement; Reconfigurable devices; Reconfigurable hardware; routing-conscious placement; Runtime; Vegetation
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2007.1028

We describe algorithmic results on two crucial aspects of allocating resources on computational hardware devices with partial reconfigurability. By using methods from the field of computational geometry, we derive a method that allows correct maintenance of free and occupied space of a set of n rectangular modules in time O(n log n); previous approaches needed a time of O(n 2 ) for correct results and O(n) for heuristic results. We also show a matching lower bound of Omega (n log n), so our approach is optimal. We also show that finding an optimal feasible communication-conscious placement (which minimizes the total weighted Manhattan distance between the new module and existing demand points) can be computed with Theta(n log n). Both resulting algorithms are practically easy to implement and show convincing experimental behavior