Low-Latency Digit-Serial Systolic Double Basis Multiplier over \mbi GF) Using Subquadratic Toeplitz Matrix-Vector Product Approach

• Published in: IEEE transactions on computers 2014-05, Vol.63 (5), p.1169-1181
• Main Authors: Jeng-Shyang Pan, Azarderakhsh, Reza, Kermani, Mehran Mozaffari, Chiou-Yng Lee, Wen-Yo Lee, Che Wun Chiou, Jim-Min Lin
• Format: Article
• Language: English
• Subjects: Clocks; Complexity theory; Computer architecture; digit-serial systolic multiplier; double basis; Educational institutions; Electronic mail; elliptic curve cryptography; Polynomials; Subquadratic Toeplitz matrix-vector product; Vectors
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2012.239

Recently in cryptography and security, the multipliers with subquadratic space complexity for trinomials and some specific pentanomials have been proposed. For such kind of multipliers, alternatively, we use double basis multiplication which combines the polynomial basis and the modified polynomial basis to develop a new efficient digit-serial systolic multiplier. The proposed multiplier depends on trinomials and almost equally space pentanomials (AESPs), and utilizes the subquadratic Toeplitz matrix-vector product scheme to derive a low-latency digit-serial systolic architecture. If the selected digit-size is d bits, the proposed digit-serial multiplier for both polynomials, i.e., trinomials and AESPs, requires the latency of 2⌈√{ m /d⌉, while traditional ones take at least O(⌈ m /d⌉) clock cycles. Analytical and application-specific integrated circuit (ASIC) synthesis results indicate that both the area and the time × area complexities of our proposed architecture are significantly lower than the existing digit-serial systolic multipliers.