FTCAM: An Area-Efficient Flash-Based Ternary CAM Design

This paper presents a Ternary Content-addressable Memory (TCAM) design which is based on the use of floating-gate (flash) transistors. TCAMs are extensively used in high speed IP networking, and are commonly found in routers in the internet core. Traditional TCAM ICs are built using CMOS devices, an...

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Bibliographic Details
Published in:IEEE transactions on computers 2016-08, Vol.65 (8), p.2652-2658
Main Authors: Fedorov, Viacheslav V., Abusultan, Monther, Khatri, Sunil P.
Format: Article
Language:English
Subjects:
Ash
Associative memory
circuit design
CMOS
CMOS integrated circuits
Computer architecture
Computer simulation
Delays
Flash
High speed
Internet
Microprocessors
Routers
Routing
Semiconductor devices
Tables (data)
TCAM
Transistors
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Summary:This paper presents a Ternary Content-addressable Memory (TCAM) design which is based on the use of floating-gate (flash) transistors. TCAMs are extensively used in high speed IP networking, and are commonly found in routers in the internet core. Traditional TCAM ICs are built using CMOS devices, and a single TCAM cell utilizes 17 transistors. In contrast, our TCAM cell utilizes only two flash transistors, thereby significantly reducing circuit area. We cover the chip-level architecture of the TCAM IC briefly, focusing mainly on the TCAM block which does fast parallel IP routing table lookup. Our flash-based TCAM (FTCAM) block is simulated in SPICE, and we show that it has a significantly lowered area compared to a CMOS based TCAM block, with a speed that can meet current ( \sim 400 Gb/s) data rates that are found in the internet core.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2015.2493535