Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device

A novel hierarchical fault-tolerance methodology for reconfigurable devices is presented. A bespoke multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), is introduced allowing fine-grained reconfiguration beyond any other FPGA architecture currently in existen...

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Bibliographic Details
Published in:IEEE transactions on computers 2017-06, Vol.66 (6), p.930-945
Main Authors: Trefzer, Martin A., Lawson, David M. R., Bale, Simon J., Walker, James A., Tyrrell, Andy M.
Format: Article
Language:English
Subjects:
Circuit faults
Circuits
Computer architecture
Fabrics
Fault location
Fault tolerance
Field programmable gate arrays
FPGA
Maintenance engineering
Performance of Systems
Reconfigurable Computing Architectures
Reconfigurable Hardware
Reconfiguration
Recovery
Repair
Routing
Special-Purpose and Application-Based Systems
Transistors
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Summary:A novel hierarchical fault-tolerance methodology for reconfigurable devices is presented. A bespoke multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), is introduced allowing fine-grained reconfiguration beyond any other FPGA architecture currently in existence. Fault blind circuit repair strategies, which require no specific information of the nature or location of faults, are developed, exploiting architectural features of PAnDA. Two fault recovery techniques, stochastic and deterministic strategies, are proposed and results of each, as well as a comparison of the two, are presented. Both approaches are based on creating algorithms performing fine-grained hierarchical partial reconfiguration on faulty circuits in order to repair them. While the stochastic approach provides insights into feasibility of the method, the deterministic approach aims to generate optimal repair strategies for generic faults induced into a specific circuit. It is shown that both techniques successfully repair the benchmark circuits used after random faults are induced in random circuit locations, and the deterministic strategies are shown to operate efficiently and effectively after optimisation for a specific use case. The methods are shown to be generally applicable to any circuit on PAnDA, and to be straightforwardly customisable for any FPGA fabric providing some regularity and symmetry in its structure.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2016.2632722