An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array

• Published in: IEEE transactions on computers 2023-12, Vol.72 (12), p.3416-3430
• Main Authors: Zhang, Sunrui, Cui, Xiaole, Wei, Feng, Cui, Xiaoxin
• Format: Article
• Language: English
• Subjects: Arbitrary Boolean functions; Arrays; Boolean; Boolean functions; Circuits; Computer architecture; Consumption; in-memory computing; Logic; Logic functions; Merging; MOS devices; Parallel processing; Performance evaluation; Random access memory; SRAM; SRAM cells; Static random access memory; synthesis method; Table lookup
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2023.3301156

In-memory computing is an emerging computing paradigm to breakthrough the von-Neumann bottleneck. The SRAM based in-memory computing (SRAM-IMC) attracts great concerns from industries and academia, because the SRAM is technology compatible with the widely-used MOS devices. The digital SRAM-IMC scheme has advantages on stability and accuracy of computing results, compared with the analog SRAM-IMC schemes. However, few logic operations can be implemented by the current digital SRAM-IMC architectures. Designers have to insert some special logic modules to facilitate the complex computation. To address this issue, this work proposes an area-efficient implementation method of arbitrary Boolean function in SRAM array. Firstly, a two-input SRAM LUT is designed to realize the arbitrary two-input Boolean functions. Then, the logic merging and the spatial merging techniques are proposed to reduce the area consumption of the SRAM-IMC scheme. Finally, the SOP-based SRAM-IMC architecture is proposed, and the merged SOPs are mapped into and computed in it. The evaluation results on LGsynth'91, IWLS'93 and EPFL benchmarks show that, the area of the synthesis results based on the ABC tool is 3.69, 5.72 and 1.86 times of the circuit area from the proposed SRAM-IMC scheme in average respectively. Furthermore, the circuit area from the original SOP-based SRAM-IMC scheme is 2.07, 1.99 and 1.86 times in average of the circuit area from the proposed SRAM-IMC scheme respectively. The performance evaluation results show that the cycle consumption of the proposed SRAM-IMC scheme is independent to the scale of the input Boolean functions.