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NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems
Random number generation is essential for applications in simulation, numerical analysis, and data encryption. The ubiquitous presence of system-on-chip (SoC) field-programmable gate array (FPGA) embedded devices in critical sectors necessitates robust random number generators (RNGs) that operate wi...
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Published in: | IEEE transactions on computers 2024-05, Vol.73 (5), p.1313-1326 |
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creator | Chen, Yucong Tian, Yanshan Zhou, Rui Martinez Castro, Diego Guo, Deke Zhou, Qingguo |
description | Random number generation is essential for applications in simulation, numerical analysis, and data encryption. The ubiquitous presence of system-on-chip (SoC) field-programmable gate array (FPGA) embedded devices in critical sectors necessitates robust random number generators (RNGs) that operate within these specialized environments. Traditional RNGs in GNU/Linux systems derive entropy from peripheral hardware events, which are scarce in SoC FPGA platforms lacking standard PC peripherals. Addressing this challenge, this paper proposes a novel random number generator named NDSTRNG that leverages the unique hardware structure of the SoC FPGA and the inherent randomness of GNU/Linux. The proposed generator employs a non-deterministic sampling model to circumvent reliance on various peripherals while ensuring unbiased output via a linear feedback shift register (LFSR)-based post-processing method. We implement this random number generator in SoC FPGA GNU/Linux using minimal FPGA resources and only one Linux task for sampling. NDSTRNG achieved a throughput exceeding 700 Kbps. Moreover, the entropy source of the generator is evaluated using NIST SP 800-90B, while the quality of the generated random numbers is assessed through ENT, NIST SP 800-22, and DIEHARDER. The results confirm that NDSTRNG meets the stringent criteria for both high-quality and high-speed random number generation, making it suitable for deployment in communication, defense, and medical domains where reliable RNGs are indispensable. |
doi_str_mv | 10.1109/TC.2024.3365955 |
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fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TC_2024_3365955</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10436529</ieee_id><sourcerecordid>3035278181</sourcerecordid><originalsourceid>FETCH-LOGICAL-c244t-6d12910e21ac6998d430c2b3fb91cd9b789364c0a64068d1f980fcd11eef6e733</originalsourceid><addsrcrecordid>eNpNkE1Pg0AURSdGE2t17cbFJK5p33wwMO6U2mrSoCm4cUMGeBiaAnUGFv330rQLV29xz70vOYTcM5gxBnqeRjMOXM6EUL72_QsyYb4feFr76pJMAFjoaSHhmtw4twUAxUFPyHe8SNJNvHqicdd6C-zRNnVbu74uaGKa_a5uf7wX47CkqR2Qbkxbdg2NhyZHS1fYojV9Z2nX0qSL6PJz9UyTg-uxcbfkqjI7h3fnOyVfy9c0evPWH6v36HntFVzK3lMl45oBcmYKpXVYSgEFz0WVa1aUOg9CLZQswCgJKixZpUOoipIxxEphIMSUPJ5297b7HdD12bYbbDu-zAQInwchC9lIzU9UYTvnLFbZ3taNsYeMQXYUmKVRdhSYnQWOjYdTo0bEf7Qcc67FH58Uago</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>3035278181</pqid></control><display><type>article</type><title>NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Chen, Yucong ; Tian, Yanshan ; Zhou, Rui ; Martinez Castro, Diego ; Guo, Deke ; Zhou, Qingguo</creator><creatorcontrib>Chen, Yucong ; Tian, Yanshan ; Zhou, Rui ; Martinez Castro, Diego ; Guo, Deke ; Zhou, Qingguo</creatorcontrib><description>Random number generation is essential for applications in simulation, numerical analysis, and data encryption. The ubiquitous presence of system-on-chip (SoC) field-programmable gate array (FPGA) embedded devices in critical sectors necessitates robust random number generators (RNGs) that operate within these specialized environments. Traditional RNGs in GNU/Linux systems derive entropy from peripheral hardware events, which are scarce in SoC FPGA platforms lacking standard PC peripherals. Addressing this challenge, this paper proposes a novel random number generator named NDSTRNG that leverages the unique hardware structure of the SoC FPGA and the inherent randomness of GNU/Linux. The proposed generator employs a non-deterministic sampling model to circumvent reliance on various peripherals while ensuring unbiased output via a linear feedback shift register (LFSR)-based post-processing method. We implement this random number generator in SoC FPGA GNU/Linux using minimal FPGA resources and only one Linux task for sampling. NDSTRNG achieved a throughput exceeding 700 Kbps. Moreover, the entropy source of the generator is evaluated using NIST SP 800-90B, while the quality of the generated random numbers is assessed through ENT, NIST SP 800-22, and DIEHARDER. The results confirm that NDSTRNG meets the stringent criteria for both high-quality and high-speed random number generation, making it suitable for deployment in communication, defense, and medical domains where reliable RNGs are indispensable.</description><identifier>ISSN: 0018-9340</identifier><identifier>EISSN: 1557-9956</identifier><identifier>DOI: 10.1109/TC.2024.3365955</identifier><identifier>CODEN: ITCOB4</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Central Processing Unit ; Data encryption ; Embedded systems ; Entropy ; Field programmable gate arrays ; Generators ; Hardware ; inherent non-determinism ; Jitter ; latency jitter ; Linear feedback shift registers ; Linux ; Numerical analysis ; Random number generator ; Random numbers ; Robustness (mathematics) ; Sampling ; SoC FPGA ; System on chip ; Throughput</subject><ispartof>IEEE transactions on computers, 2024-05, Vol.73 (5), p.1313-1326</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c244t-6d12910e21ac6998d430c2b3fb91cd9b789364c0a64068d1f980fcd11eef6e733</cites><orcidid>0000-0002-6038-7249 ; 0000-0003-4894-5540 ; 0000-0002-2618-0834 ; 0000-0003-0555-9199 ; 0000-0001-8054-5446</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10436529$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Chen, Yucong</creatorcontrib><creatorcontrib>Tian, Yanshan</creatorcontrib><creatorcontrib>Zhou, Rui</creatorcontrib><creatorcontrib>Martinez Castro, Diego</creatorcontrib><creatorcontrib>Guo, Deke</creatorcontrib><creatorcontrib>Zhou, Qingguo</creatorcontrib><title>NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems</title><title>IEEE transactions on computers</title><addtitle>TC</addtitle><description>Random number generation is essential for applications in simulation, numerical analysis, and data encryption. The ubiquitous presence of system-on-chip (SoC) field-programmable gate array (FPGA) embedded devices in critical sectors necessitates robust random number generators (RNGs) that operate within these specialized environments. Traditional RNGs in GNU/Linux systems derive entropy from peripheral hardware events, which are scarce in SoC FPGA platforms lacking standard PC peripherals. Addressing this challenge, this paper proposes a novel random number generator named NDSTRNG that leverages the unique hardware structure of the SoC FPGA and the inherent randomness of GNU/Linux. The proposed generator employs a non-deterministic sampling model to circumvent reliance on various peripherals while ensuring unbiased output via a linear feedback shift register (LFSR)-based post-processing method. We implement this random number generator in SoC FPGA GNU/Linux using minimal FPGA resources and only one Linux task for sampling. NDSTRNG achieved a throughput exceeding 700 Kbps. Moreover, the entropy source of the generator is evaluated using NIST SP 800-90B, while the quality of the generated random numbers is assessed through ENT, NIST SP 800-22, and DIEHARDER. The results confirm that NDSTRNG meets the stringent criteria for both high-quality and high-speed random number generation, making it suitable for deployment in communication, defense, and medical domains where reliable RNGs are indispensable.</description><subject>Central Processing Unit</subject><subject>Data encryption</subject><subject>Embedded systems</subject><subject>Entropy</subject><subject>Field programmable gate arrays</subject><subject>Generators</subject><subject>Hardware</subject><subject>inherent non-determinism</subject><subject>Jitter</subject><subject>latency jitter</subject><subject>Linear feedback shift registers</subject><subject>Linux</subject><subject>Numerical analysis</subject><subject>Random number generator</subject><subject>Random numbers</subject><subject>Robustness (mathematics)</subject><subject>Sampling</subject><subject>SoC FPGA</subject><subject>System on chip</subject><subject>Throughput</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><recordid>eNpNkE1Pg0AURSdGE2t17cbFJK5p33wwMO6U2mrSoCm4cUMGeBiaAnUGFv330rQLV29xz70vOYTcM5gxBnqeRjMOXM6EUL72_QsyYb4feFr76pJMAFjoaSHhmtw4twUAxUFPyHe8SNJNvHqicdd6C-zRNnVbu74uaGKa_a5uf7wX47CkqR2Qbkxbdg2NhyZHS1fYojV9Z2nX0qSL6PJz9UyTg-uxcbfkqjI7h3fnOyVfy9c0evPWH6v36HntFVzK3lMl45oBcmYKpXVYSgEFz0WVa1aUOg9CLZQswCgJKixZpUOoipIxxEphIMSUPJ5297b7HdD12bYbbDu-zAQInwchC9lIzU9UYTvnLFbZ3taNsYeMQXYUmKVRdhSYnQWOjYdTo0bEf7Qcc67FH58Uago</recordid><startdate>20240501</startdate><enddate>20240501</enddate><creator>Chen, Yucong</creator><creator>Tian, Yanshan</creator><creator>Zhou, Rui</creator><creator>Martinez Castro, Diego</creator><creator>Guo, Deke</creator><creator>Zhou, Qingguo</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><orcidid>https://orcid.org/0000-0002-6038-7249</orcidid><orcidid>https://orcid.org/0000-0003-4894-5540</orcidid><orcidid>https://orcid.org/0000-0002-2618-0834</orcidid><orcidid>https://orcid.org/0000-0003-0555-9199</orcidid><orcidid>https://orcid.org/0000-0001-8054-5446</orcidid></search><sort><creationdate>20240501</creationdate><title>NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems</title><author>Chen, Yucong ; Tian, Yanshan ; Zhou, Rui ; Martinez Castro, Diego ; Guo, Deke ; Zhou, Qingguo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c244t-6d12910e21ac6998d430c2b3fb91cd9b789364c0a64068d1f980fcd11eef6e733</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Central Processing Unit</topic><topic>Data encryption</topic><topic>Embedded systems</topic><topic>Entropy</topic><topic>Field programmable gate arrays</topic><topic>Generators</topic><topic>Hardware</topic><topic>inherent non-determinism</topic><topic>Jitter</topic><topic>latency jitter</topic><topic>Linear feedback shift registers</topic><topic>Linux</topic><topic>Numerical analysis</topic><topic>Random number generator</topic><topic>Random numbers</topic><topic>Robustness (mathematics)</topic><topic>Sampling</topic><topic>SoC FPGA</topic><topic>System on chip</topic><topic>Throughput</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chen, Yucong</creatorcontrib><creatorcontrib>Tian, Yanshan</creatorcontrib><creatorcontrib>Zhou, Rui</creatorcontrib><creatorcontrib>Martinez Castro, Diego</creatorcontrib><creatorcontrib>Guo, Deke</creatorcontrib><creatorcontrib>Zhou, Qingguo</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) Online</collection><collection>IEEE</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chen, Yucong</au><au>Tian, Yanshan</au><au>Zhou, Rui</au><au>Martinez Castro, Diego</au><au>Guo, Deke</au><au>Zhou, Qingguo</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems</atitle><jtitle>IEEE transactions on computers</jtitle><stitle>TC</stitle><date>2024-05-01</date><risdate>2024</risdate><volume>73</volume><issue>5</issue><spage>1313</spage><epage>1326</epage><pages>1313-1326</pages><issn>0018-9340</issn><eissn>1557-9956</eissn><coden>ITCOB4</coden><abstract>Random number generation is essential for applications in simulation, numerical analysis, and data encryption. The ubiquitous presence of system-on-chip (SoC) field-programmable gate array (FPGA) embedded devices in critical sectors necessitates robust random number generators (RNGs) that operate within these specialized environments. Traditional RNGs in GNU/Linux systems derive entropy from peripheral hardware events, which are scarce in SoC FPGA platforms lacking standard PC peripherals. Addressing this challenge, this paper proposes a novel random number generator named NDSTRNG that leverages the unique hardware structure of the SoC FPGA and the inherent randomness of GNU/Linux. The proposed generator employs a non-deterministic sampling model to circumvent reliance on various peripherals while ensuring unbiased output via a linear feedback shift register (LFSR)-based post-processing method. We implement this random number generator in SoC FPGA GNU/Linux using minimal FPGA resources and only one Linux task for sampling. NDSTRNG achieved a throughput exceeding 700 Kbps. Moreover, the entropy source of the generator is evaluated using NIST SP 800-90B, while the quality of the generated random numbers is assessed through ENT, NIST SP 800-22, and DIEHARDER. The results confirm that NDSTRNG meets the stringent criteria for both high-quality and high-speed random number generation, making it suitable for deployment in communication, defense, and medical domains where reliable RNGs are indispensable.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TC.2024.3365955</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0002-6038-7249</orcidid><orcidid>https://orcid.org/0000-0003-4894-5540</orcidid><orcidid>https://orcid.org/0000-0002-2618-0834</orcidid><orcidid>https://orcid.org/0000-0003-0555-9199</orcidid><orcidid>https://orcid.org/0000-0001-8054-5446</orcidid></addata></record> |
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subjects | Central Processing Unit Data encryption Embedded systems Entropy Field programmable gate arrays Generators Hardware inherent non-determinism Jitter latency jitter Linear feedback shift registers Linux Numerical analysis Random number generator Random numbers Robustness (mathematics) Sampling SoC FPGA System on chip Throughput |
title | NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T11%3A04%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=NDSTRNG:%20Non-Deterministic%20Sampling-Based%20True%20Random%20Number%20Generator%20on%20SoC%20FPGA%20Systems&rft.jtitle=IEEE%20transactions%20on%20computers&rft.au=Chen,%20Yucong&rft.date=2024-05-01&rft.volume=73&rft.issue=5&rft.spage=1313&rft.epage=1326&rft.pages=1313-1326&rft.issn=0018-9340&rft.eissn=1557-9956&rft.coden=ITCOB4&rft_id=info:doi/10.1109/TC.2024.3365955&rft_dat=%3Cproquest_cross%3E3035278181%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c244t-6d12910e21ac6998d430c2b3fb91cd9b789364c0a64068d1f980fcd11eef6e733%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=3035278181&rft_id=info:pmid/&rft_ieee_id=10436529&rfr_iscdi=true |