Stress Current Slew Rate Sensitivity of an Ultra-High-Speed Interface IC

This study analyzes the Electrostatic Discharge (ESD) susceptibility of a 28nm high-speed CMOS Integrated Circuit (IC) for network applications (25Gbps), showing a non-negligible failure rate in manufacturing after having passed Charged Device Model (CDM) qualification testing. A detailed inspection...

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Bibliographic Details
Published in:IEEE transactions on device and materials reliability 2019-12, Vol.19 (4), p.591-601
Main Authors: Weber, Johannes, Fung, Rita, Wong, Richard, Wolf, Heinrich, Gieser, Horst A., Maurer, Linus
Format: Magazinearticle
Language:English
Subjects:
Capacitively coupled transmission line pulsing (CC-TLP)
charged device model (CDM)
Circuit boards
CMOS
Connectors
correlation study
critical stress parameters
DC-blocking capacitor
Discharges (electric)
Electrostatic discharges
electrostatic discharges (ESD)
Embedding
Failure rates
High speed
Inspection
Integrated circuits
Model testing
Pins
Printed circuits
rise time
Sensitivity analysis
Slew rate
Standardization
Stress
Testing
Transmission lines
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Summary:This study analyzes the Electrostatic Discharge (ESD) susceptibility of a 28nm high-speed CMOS Integrated Circuit (IC) for network applications (25Gbps), showing a non-negligible failure rate in manufacturing after having passed Charged Device Model (CDM) qualification testing. A detailed inspection of each process step identified the press-fit assembly of charged through-hole connectors to be the root cause for ultra-fast discharges through the Printed Circuit Board (PCB) traces into the high-speed RF interface. Extended CDM tests of the high-speed ICs displayed a wide overlap of pass and fail not allowing for a clear conclusion regarding the CDM robustness. Only the single digit ps-resolution and precision of the highly reproducible test method Capacitively Coupled Transmission Line Pulsing (CC-TLP) allowed a conclusive sharp pass/fail transition at a certain peak current level. In combination with a 33/63GHz single shot oscilloscope, it eventually identified the stress current slew rate to have a direct influence on the failure threshold, explaining the non-conclusive failure distribution of CDM. For this result, we had to increase the bandwidth of the CC-TLP setup, challenge the limits of today's metrology and test setups, and implement post measurement embedding/de-embedding techniques. By pushing the frontiers of today's ESD testing in the CDM domain, the outcome of this study should contribute to future standardization of CDM and CC-TLP.
ISSN:1530-4388
1558-2574
DOI:10.1109/TDMR.2019.2952286