Fermi-level pinning at the polysilicon/metal-oxide interface-Part II

We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2004-06, Vol.51 (6), p.978-984
Main Authors: Hobbs, C.C., Fonseca, L.R.C., Knizhnik, A., Dhandapani, V., Samavedam, S.B., Taylor, W.J., Grant, J.M., Dip, L.G., Triyoso, D.H., Hegde, R.I., Gilmer, D.C., Garcia, R., Roan, D., Lovejoy, M.L., Rai, R.S., Hebert, E.A., Hsing-Huang Tseng, Anderson, S.G.H., White, B.E., Tobin, P.J.
Format: Article
Language:English
Subjects:
Aluminum compounds
Aluminum oxide
CVD
Deposition
Devices
Hafnium compounds
Hafnium oxide
Interface phenomena
Metal oxides
MOSFETs
Pinning
Semiconductor device modeling
Semiconductor-insulator interfaces
Silicon
Threshold voltage
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Summary:We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2004.829510