Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration

Optical chip-to-chip communication is a promising technology that can mitigate some of the performance short-comings of electrical interconnections, especially bandwidth. Moreover, future high-performance chips are projected to drain hundreds of amperes of supply current. To this end, it is importan...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2004-07, Vol.51 (7), p.1069-1077
Main Authors: Bakir, M.S., Meindl, J.D.
Format: Article
Language:English
Subjects:
Charge carrier mobility
Chips
Devices
Dielectrics
Drains
Interconnections
MESFET integrated circuits
Monte Carlo methods
Pillars
Semiconductor device modeling
Silicon compounds
Surface area
Thermal cycling
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Summary:Optical chip-to-chip communication is a promising technology that can mitigate some of the performance short-comings of electrical interconnections, especially bandwidth. Moreover, future high-performance chips are projected to drain hundreds of amperes of supply current. To this end, it is important to develop a high-density and high-performance integrated electrical and optical chip I/O interconnection technology. We describe sea of polymer pillars (or polymer pins), which enables the simultaneous batch fabrication of electrical and optical I/O interconnections at the wafer-level. The electrical and optical I/O interconnections are designed to be laterally compliant to minimize the stresses on the die's low-k dielectric as well as to maintain optical alignment between the coefficient of thermal expansion (CTE)-mismatched board and die during thermal cycling. We demonstrate the fabrication and mechanical performance of various size and aspect ratio electrical and optical polymer pillars. We also describe methods of fabricating polymer pillars with nonflat tip surface area for optical interconnection.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2004.829865