Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test

The physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been cl...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2005-08, Vol.52 (8), p.1821-1831
Main Authors: KER, Ming-Dou, HSU, Sheng-Fu
Format: Article
Language:English
Subjects:
Applied sciences
Chip formation
CMOS
CMOS integrated circuits
Design. Technologies. Operation analysis. Testing
Devices
Electric potential
Electronics
Electrostatic discharges
Exact sciences and technology
Holding voltage
Integrated circuit testing
Integrated circuits
latchup
Minority carriers
Other multijunction devices. Power transistors. Thyristors
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
silicon controlled rectifier (SCR)
Simulation
system-level electrostatic discharge (ESD) test
Time domain analysis
transient-induced latchup (TLU)
Voltage
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Summary:The physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific "sweep-back" current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated by 0.25-/spl mu/m CMOS technology.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2005.852728