Numerical Study of Flicker Noise in p-Type \hbox\hbox/\hbox Heterostructure MOSFETs

Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si 0.7 Ge 0.3 /Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a lay...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2008-07, Vol.55 (7), p.1741-1748
Main Authors: Chen, Chia-Yu, Liu, Yang, Dutton, Robert W., Sato-Iwanaga, Junko, Inoue, Akira, Sorada, Haruyuki
Format: Article
Language:English
Subjects:
1/f noise
Flicker noise
heterostructure
Logic gates
Low-frequency noise
Mathematical model
MOSFET
MOSFETs
Numerical models
SiGe
Silicon
Silicon germanium
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Summary:Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si 0.7 Ge 0.3 /Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2008.925329