Insights on Design and Scalability of Thin-BOX FD/SOI CMOS

Device simulations are used to gain insights on the design of nanoscale thin-buried-oxide (and ultrathin-body) fully depleted/silicon-on-insulator (SOI) CMOS and to assess its scalability toward the end of the Semiconductor Industry Association roadmap (International Technology Roadmap for Semicondu...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2010-09, Vol.57 (9), p.2073-2079
Main Authors: Chouksey, S, Fossum, J G, Agrawal, S
Format: Article
Language:English
Subjects:
Applied sciences
CMOS integrated circuits
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
FinFETs
General (including economical and industrial fields)
high-performance (HP) CMOS
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic gates
low-power (LP) CMOS
MOSFET circuits
planar fully depleted (FD)/silicon-on-insulator (SOI) MOSFETs
Scalability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon on insulator technology
static random access memory (SRAM)
Transistors
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Summary:Device simulations are used to gain insights on the design of nanoscale thin-buried-oxide (and ultrathin-body) fully depleted/silicon-on-insulator (SOI) CMOS and to assess its scalability toward the end of the Semiconductor Industry Association roadmap (International Technology Roadmap for Semiconductors), relative to that of FinFET CMOS. The simulation results imply, albeit with complex processing, good scalability and performance for low-power (LP) applications (including static random access memory), defined by minimum viable SOI thickness. However, the scalability for high-performance (HP) applications is limited, but the processing can be simplified. Results for double-gate FinFETs are better, showing good scalability and performance to the end of the ITRS for both HP and LP applications.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2010.2052420