Scaling SOI MESFETs to 150-nm CMOS Technologies

Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an e...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2011-06, Vol.58 (6), p.1628-1634
Main Authors: Lepkowski, W, Ghajar, M R, Wilk, S J, Summers, N, Thornton, T J, Fechner, P S
Format: Article
Language:English
Subjects:
Applied sciences
CMOS
CMOS integrated circuits
CMOS process
Depletion
Design. Technologies. Operation analysis. Testing
Devices
Electric breakdown
Electronics
Exact sciences and technology
Gates
Integrated circuits
Layout
Logic gates
MESFETs
Metal-semiconductor field-effect transistors (MESFETs)
Optimization
partially depleted (PD)
Schottky junction
Semiconductor devices
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
silicon-on-insulator (SOI)
Transistors
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Summary:Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with L g = 150 nm have a current drive that exceeds 200 mA/mm with a peak f T >; 35 GHz. This is considerably higher than the L g = 400 nm MESFET with a current drive of ~70 mA/mm and a peak f T = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for L g
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2011.2125965