Considerations for Ultimate CMOS Scaling

This review paper explores considerations for ultimate CMOS transistor scaling. Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted. Key...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2012-07, Vol.59 (7), p.1813-1828
Main Author: Kuhn, K. J.
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance
CMOS integrated circuits
Complementary metal-oxide semiconductor (CMOS)
Cross-disciplinary physics: materials science
rheology
Design. Technologies. Operation analysis. Testing
Electronics
Electrostatics
Exact sciences and technology
FinFET
Integrated circuits
Logic gates
Materials
Materials science
Metals
mobility
Nanoscale materials and structures: fabrication and characterization
nanowire
Physics
Quantum wires
Resistance
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
silicon on insulator (SOI)
strain
Transistors
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Summary:This review paper explores considerations for ultimate CMOS transistor scaling. Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted. Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2012.2193129