Hybrid Open Drain Method and Fully Current-Based Characterization of Asymmetric Resistance Components in a Single MOSFET

• Published in: IEEE transactions on electron devices 2016-11, Vol.63 (11), p.4196-4200
• Main Authors: Kim, Jaewon, Lee, Heesung, Kim, Seong Kwang, Kim, Junyeap, Park, Jaewon, Choi, Sung-Jin, Kim, Dae Hwan, Kim, Dong Myong
• Format: Article
• Language: English
• Subjects: Customer relationship management; Degradation; Drain resistance; Integrated circuit modeling; MOSFET; open drain method (ODM); Resistance; separate extraction; single MOSFET; source resistance; substrate resistance; Substrates; Transconductance
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2016.2607721

Separate extraction of source (RS) from drain resistance (RD) is important in the systematic modeling of electrical characteristics and investigation of physical mechanism related to the performance and reliability in MOSFETs and their integrated circuits. We report a hybrid open drain method (ODM), as a fully current-based characterization technique, for a comprehensive separation of asymmetric source and drain resistance components in a single MOSFET. In the hybrid ODM, the ODM through the parasitic bipolar transistor is combined with the dual-sweep combinational transconductance technique, the channel resistance method, and the parasitic junction current method. We fully considered the asymmetry in the source and the drain possibly caused by the layout, process, and degradation under bias. We successfully extracted the resistance components with R Se = 6.66-7.35 Q, R De = 7.64-8.34 Q, R So = 0.78-8.07 Q, R Do = 1.11-10.08 Q, and R SUB = 6.29-9.17 Q in the n-channel MOSFETs. R Se (R De ) is the V GS -independent external source (drain) resistance. R So (R Do ) is the VGS-independent external spreading source (drain) resistance and R Si (R Di ) is the V GS -dependent intrinsic source (drain) resistance, respectively. R SUB is the substrate resistance. The hybrid ODM is expected to be useful in the characterization of parasitic resistances in each MOSFET with asymmetry caused by the layout, process, and degradation without using multiple devices with different channel length (L) and width (W) for measurement.