Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs

• Published in: IEEE transactions on electron devices 2017-07, Vol.64 (7), p.2992-2998
• Main Authors: Hsieh, Dong-Ru, Lin, Jer-Yi, Kuo, Po-Yi, Chao, Tien-Sheng
• Format: Article
• Language: English
• Subjects: Carrier density; Carrier mobility; channel dimension; Channels; Circuits; Crystallinity; Devices; effective carrier concentration; Fabrication; Field effect transistors; High aspect ratio; Integrated circuits; junctionless (JL); Logic gates; multifunctional 3-D ICs; Phosphorus; Pi-gate (PG); poly-Si; Silicon films; Threshold voltage
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2017.2704933

In this paper, the electrical characteristics of the Pi-gate junctionless FETs (PG JL FETs) with the in situ n + doped poly-Si (DP-Si) fin-channels have been experimentally investigated and comprehensively discussed. The subthreshold behavior and threshold voltage of the PG JL FETs are sensitive to the channel dimensions, especially the channel width. The crystallinity, carrier mobility, and effective carrier concentration in the DP-Si films are dependent on the initial DP-Si film thicknesses, which directly influence the on current and threshold voltage of the PG JL FETs. Based on an evaluation on the subthreshold behavior and the driving current, we found that the PG JL FETs with the low/high aspect ratio (A.R. = channel thickness/channel width) are separately suitable for the low-power/high-performanceapplications.Among these PG JL FETs, the device with a proper A.R. (3.35) exhibits a relatively steep subthreshold swing (S.S.) of 66 mV/decade and the highest ON/OFF currents ratio (I ON /I OFF ) of 1.2 × 10 8 (V D = 1 V). These devices are very promising candidates for future multifunctional 3-D integrated circuit applications.