Embedding Statistical Variability Into Propagation Delay Time Compact Models Using Different Parameter Sets: A Comparative Study in 35-nm Technology

• Published in: IEEE transactions on electron devices 2018-07, Vol.65 (7), p.2714-2720
• Main Authors: Jooypa, Hamed, Dideban, Daryoosh
• Format: Article
• Language: English
• Subjects: Analytical models; Compact models (CMs); Integrated circuit modeling; Inverters; Mathematical model; nano-CMOS; nano-MOSFETs; Numerical models; Propagation delay; propagation delay time; Semiconductor device modeling; statistical variability (SV)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2018.2833879

With shrinking transistor dimensions into sub-50-nm regime, statistical variability (SV) causes a great impact on the drain current and threshold voltage of nano-MOSFETs. In this paper, with emphasis on the propagation delay time of an inverter in 35-nm technology node, we have first introduced a strategy to take SV into account in four existing compact models using different number of statistical sets. For each model under study, we identified effective parameters of analytical equations which can be utilized to replicate the impact of SV. Moreover, we analyzed the statistical distribution and correlation of those effective parameters and their impact on the propagation delay time in each model. The results of these statistical CMs are compared with the accurate "atomistic" model, and it is shown that using this approach we can predict the propagation delay time standard deviation with less than 0.2%, 4.1%, 4.8%, and 4.7% errors in different models. However, the mean values of the propagation delay time stay almost constant even by employing statistical sets of single parameters. Furthermore, we study the impact of changing the load capacitance and the supply voltage on the statistical behavior of four models in the presence of SV.