Avalanche Ruggedness Capability and Improvement of 5-V n-Channel Large-Array MOSFET in BCD Process

• Published in: IEEE transactions on electron devices 2019-07, Vol.66 (7), p.3040-3048
• Main Authors: Nidhi, Karuna, Ker, Ming-Dou, Lee, Jian-Hsing, Huang, Shao-Chang
• Format: Article
• Language: English
• Subjects: Arrays; Avalanche ruggedness; avalanche safe-operating-area (A-SOA); Avalanches; CMOS; current in avalanche (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">I AV); Failure analysis; Implantation; Inductors; large-array device (LAD); Layout; Logic gates; MOSFET; MOSFETs; Performance evaluation; Ruggedness; Switches; time in avalanche (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">t AV); total gate charge (Qg); unclamped inductive switching (UIS); Voltage measurement
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2019.2916032

Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current ( {I}_{\text {AV}} ) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12 000~\mu \text{m} .