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Drain-Extended FinFET With Embedded SCR (DeFinFET-SCR) for High-Voltage ESD Protection and Self-Protected Designs
This article presents device design insights and design challenges for drain-extended FinFET devices with embedded silicon-controlled rectifier (SCR) (DeFinFET-SCR), which can be used as an electrostatic discharge (ESD) protection device and a self-protected high-voltage switch/driver for system-on-...
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Published in: | IEEE transactions on electron devices 2019-12, Vol.66 (12), p.5072-5079 |
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container_end_page | 5079 |
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container_title | IEEE transactions on electron devices |
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creator | Paul, Milova Sampath Kumar, B. Karmel Nagothu, Kranthi Singhal, Pulkit Gossner, Harald Shrivastava, Mayank |
description | This article presents device design insights and design challenges for drain-extended FinFET devices with embedded silicon-controlled rectifier (SCR) (DeFinFET-SCR), which can be used as an electrostatic discharge (ESD) protection device and a self-protected high-voltage switch/driver for system-on-chip applications. The tradeoff between maximizing ESD robustness without hindering the transistor's operation is discussed in detail. An interplay between parasitic p-n-p turn-on and space charge modulation (SCM) is revealed, which strongly influences the strength of parasitic SCR and its turn-on efficiency during ESD and DC operations. Developed physical insights show that engineering p-n-p turn-on and onset of SCM are the key to maximize ESD robustness without causing early SCR turn-on during transistor operation. Based on new findings and developed physical insights, design guidelines have been derived for ESD robust DeFinFET-SCR. |
doi_str_mv | 10.1109/TED.2019.2949126 |
format | article |
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The tradeoff between maximizing ESD robustness without hindering the transistor's operation is discussed in detail. An interplay between parasitic p-n-p turn-on and space charge modulation (SCM) is revealed, which strongly influences the strength of parasitic SCR and its turn-on efficiency during ESD and DC operations. Developed physical insights show that engineering p-n-p turn-on and onset of SCM are the key to maximize ESD robustness without causing early SCR turn-on during transistor operation. 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The tradeoff between maximizing ESD robustness without hindering the transistor's operation is discussed in detail. An interplay between parasitic p-n-p turn-on and space charge modulation (SCM) is revealed, which strongly influences the strength of parasitic SCR and its turn-on efficiency during ESD and DC operations. Developed physical insights show that engineering p-n-p turn-on and onset of SCM are the key to maximize ESD robustness without causing early SCR turn-on during transistor operation. Based on new findings and developed physical insights, design guidelines have been derived for ESD robust DeFinFET-SCR.</description><subject>Anodes</subject><subject>Charge carrier processes</subject><subject>Drain-extended FinFET (DeFinFET)</subject><subject>electrostatic discharge (ESD)</subject><subject>Electrostatic discharges</subject><subject>FinFETs</subject><subject>High voltages</subject><subject>Modulation</subject><subject>Robustness</subject><subject>Semiconductor devices</subject><subject>Silicon controlled rectifiers</subject><subject>silicon-controlled rectifier (SCR)</subject><subject>Space charge</subject><subject>Static electricity</subject><subject>Stress</subject><subject>System on chip</subject><subject>technology computer-aided design (TCAD)</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><recordid>eNo9kM1Lw0AQxRdRsFbvgpcFL3rYul9Jdo7SpFYoKLbqcdkku21Km7SbFPS_d0uKp-HNvPcGfgjdMjpijMLTIktHnDIYcZDAeHyGBiyKEgKxjM_RgFKmCAglLtFV266DjKXkA7RPvalqkv10ti5tiSdVPckW-LvqVjjb5rY8LufjD_yQ2v5GgnrErvF4Wi1X5KvZdGZpcTZP8btvOlt0VVNjU4eY3Thy2oWW1LbVsm6v0YUzm9benOYQfYbW8ZTM3l5ex88zUnBgHcmFVKBcJEzJ8yRRJQXHCmBJEVEJBlwEkRVFyV2eRCANqELkEXMl4xICCDFE933vzjf7g207vW4Ovg4vNRecKxWIxMFFe1fhm7b11umdr7bG_2pG9RGsDmD1Eaw-gQ2Ruz5SWWv_7UqBFKHwDwnBcT0</recordid><startdate>20191201</startdate><enddate>20191201</enddate><creator>Paul, Milova</creator><creator>Sampath Kumar, B.</creator><creator>Karmel Nagothu, Kranthi</creator><creator>Singhal, Pulkit</creator><creator>Gossner, Harald</creator><creator>Shrivastava, Mayank</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The tradeoff between maximizing ESD robustness without hindering the transistor's operation is discussed in detail. An interplay between parasitic p-n-p turn-on and space charge modulation (SCM) is revealed, which strongly influences the strength of parasitic SCR and its turn-on efficiency during ESD and DC operations. Developed physical insights show that engineering p-n-p turn-on and onset of SCM are the key to maximize ESD robustness without causing early SCR turn-on during transistor operation. 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subjects | Anodes Charge carrier processes Drain-extended FinFET (DeFinFET) electrostatic discharge (ESD) Electrostatic discharges FinFETs High voltages Modulation Robustness Semiconductor devices Silicon controlled rectifiers silicon-controlled rectifier (SCR) Space charge Static electricity Stress System on chip technology computer-aided design (TCAD) Transistors |
title | Drain-Extended FinFET With Embedded SCR (DeFinFET-SCR) for High-Voltage ESD Protection and Self-Protected Designs |
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