On the Trap Locations in Bulk FinFETs After Hot Carrier Degradation (HCD)

• Published in: IEEE transactions on electron devices 2020-07, Vol.67 (7), p.3005-3009
• Main Authors: Yu, Zhuoqing, Zhang, Zhe, Sun, Zixuan, Wang, Runsheng, Huang, Ru
• Format: Article
• Language: English
• Subjects: Analytical models; Degradation; Electron traps; FinFET; FinFETs; hot carrier; Hot carriers; reliability; Semiconductor process modeling; Stress; trap location; variability
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2020.2994171

In this brief, typical locations of the interface and oxide traps generated by the hot carrier degradation (HCD) in FinFETs are studied with experiments and "atomistic" TCAD simulations under the worst case stress conditions. The typical round-Fin locations of different types of traps are analyzed by comparing the experimentally extracted results with the calibrated TCAD simulations. Then, the traps' different impacts on HCD variations in both forward and reverse bias modes are employed to disclose the typical lateral locations of different traps. The results suggest that for both n- and p-type of FinFETs under the worst case stress conditions, the interface traps and oxide traps (type 1) are mainly distributed in the midchannel region closer to the source side on the Fin side, whereas oxide traps (type 2) are mainly distributed in the midchannel region closer to the drain side on the Fin top. Therefore, the two types of oxide traps originate in the different generation locations but may share the same atomistic structures in the same device. The results are helpful to the physical understandings of HCD in the FinFET technology.